1. Field of the Invention
The present invention relates to a booster circuit for digital signal transmissions, which is used by attaching it to a signal line for transmitting digital voltage signals such as in a bus line in a computer, and thereby the signal transmission speed is raised up through reducing the signal propagation delay due to load capacitance and/or load resistance of the signal line. The booster has an extremely large effect particularly when it is applied to signal lines in integrated circuits.
2. Description of the Prior Art
In a signal line in a MOS integrated circuit such as a bus line of a microcomputer, because of its comparatively large amount of parasitic capacitance and gate input capacitance and also because of a relatively high impedance of a MOS transistor used for driving the signal line, the delay of the signal propagation becomes considerably large.
FIG. 1 is a curve showing a variation of voltage on a signal line in a CMOS (complementary-MOS) integrated circuit. When any one of gates for driving the signal line makes a transition from low level to high level at a time t.sub.1, a signal appears on an input of a receiving gate with a variation of a charging curve determined mainly by a load capacitance of the signal line and an output impedance of the driving gate as shown by a broken curve in FIG. 1. The threshold voltage V.sub.TH of input and output signals is ordinarily taken to be a half value of a power supply voltage V.sub.DD. This means that the receiving gate receives a signal of "0" to "1" at a time t.sub.B at which the broken curve crosses V.sub.TH. Therefore, the propagation delay time on the signal line becomes the large time interval of t.sub.B -t.sub.1 in FIG. 1. Although this signal propagation delay time may be reduced by making line driving transistors large, in the case such as in a bus line of a microcomputer wherein a large number of input and output gates (for example, input and output gates of various registers) are connected, the enlargement of transistors of individual output gates requires extremely large area and therefore an increase in the chip size and hence an increase in the power consumption is brought about. This is an unfavorable result.